HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 285

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.4.4
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
3. When the slave address matches in the first frame following the start condition, the device
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
(master output)
(master output)
User processing
(slave output)
according to the operating mode.
to 1.
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1 and ninth clock is received for the following data receival, the slave device
drives SCL low from the falling edge of the receive clock until data is read into ICDR.
SDA
SCL
SDA
IRTR
ICDR
IRIC
Slave Receive Operation
Data 2
Bit 0
Figure 15.6 Master Receive Mode Operation Timing Example (2)
8
[9] IRIC clearance
Data 1
[8]
A
[5]
9
[6] ICDR read
(Data 2)
Bit 7
(MLS = ACKB = 0, WAIT = 1)
1
Bit 6
2
Bit 5
[7] IRIC clearance
3
Data 3
Data 2
Bit 4
4
Bit 3
5
Bit 2
6
Rev. 6.00 Mar. 24, 2006 Page 255 of 412
Bit 1
7
[9] IRIC clearance
Bit 0
Section 15 I
8
[8]
[6] ICDR read
A
2
C Bus Interface (IIC)
(Data 3)
REJ09B0142-0600
[5]
9
Data 3
[7] IRIC clearance
Bit 7
1
Data 4
Bit 6
2