HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 77

IC H8 MCU FLASH 32K 64QFP

HD64F3664H

Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664H

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
Prior to executing BSET
BSET instruction executed
After executing BSET
Input/output
Pin state
PCR5
PDR5
RAM0
Input/output
Pin state
PCR5
PDR5
RAM0
MOV.B
MOV.B
MOV.B
BSET
MOV.B
MOV.B
#80,
R0L,
R0L,
#0,
@RAM0, R0L
R0L,
P57
Input
Low
level
0
1
1
P57
Input
Low
level
0
1
1
R0L
@RAM0
@PDR5
@PDR5
@RAM0
0
0
0
0
0
0
P56
Input
High
level
P56
Input
High
level
P55
Output
Low
level
1
0
0
P55
Output
Low
level
1
0
0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
P54
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
Rev. 6.00 Mar. 24, 2006 Page 47 of 412
P52
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
REJ09B0142-0600
Section 2 CPU
P50
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1

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