HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 71

IC H8 MCU FLASH 32K 64QFP

HD64F3664H

Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664H

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H H8/3664
Manufacturer:
RENESAS
Quantity:
13
Part Number:
HD64F3664HJ
Manufacturer:
TI
Quantity:
171
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3664HV
Manufacturer:
ALTERA
Quantity:
101
Part Number:
HD64F3664HV
Manufacturer:
RENESAS
Quantity:
630
Part Number:
HD64F3664HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
2.6
CPU operation is synchronized by a system clock (φ) or a subclock (φ
edge of φ or φ
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Basic Bus Cycle
Access to On-Chip Memory (RAM, ROM)
SUB
to the next rising edge is called one state. A bus cycle consists of two states or
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
or
SUB
Figure 2.9 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Write data
Read data
T
Rev. 6.00 Mar. 24, 2006 Page 41 of 412
2
state
SUB
). The period from a rising
REJ09B0142-0600
Section 2 CPU

Related parts for HD64F3664H