HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 323

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.4.7
There are two types write operations; byte write operation and page write operation. To initiate
the write operation, input 0 to R/W code following the slave address.
1. Byte Write
2. Page Write
SCL
SDA
A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then
the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then,
two bytes of the memory address are received from the MSB side in the order of upper and
lower. Upon receipt of one-byte memory address, the EEPROM sends acknowledgement "0"
and receives a following a one-byte write data. After receipt of write data, the EEPROM sends
acknowledgement "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally controlled write cycle and terminates receipt of SCL and SDA inputs until
completion of the write cycle. The EEPROM returns to a standby mode after completion of
the write cycle.
The byte write operation is shown in figure 17.3.
This LSI is capable of the page write operation which allows any number of bytes up to 8
bytes to be written in a single write cycle. The write data is input in the same sequence as the
byte write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
condition
Start
Write Operations
1
2
3
Slave address
4
5
Figure 17.3 Byte Write Operation
6
7
R/W ACK
8
9
A15
1
Upper memory
address
A8
8
ACK
9
A7
1
Rev. 6.00 Mar. 24, 2006 Page 293 of 412
lower memory
address
A0
8
ACK
9
D7
1
Write Data
Section 17 EEPROM
REJ09B0142-0600
D0
8
ACK
9
conditon
Stop