MRF49XA-I/ST Microchip Technology, MRF49XA-I/ST Datasheet - Page 20

• Manufacturer Part Number: MRF49XA-I/ST
• Description: IC RF TXRX 433/868/915 16-TSSOP
• Manufacturer: Microchip Technology

Specifications of MRF49XA-I/ST

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FHSS, FSK
• Applications: Home / Industrial Automation, Remote Access, Security Alarms
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 11mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 2
• Wireless Frequency: 433 MHz to 915 MHz
• Output Power: + 7 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Modulation: FHSS, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 579-MRF49XA-1/ST

2.17
REGISTER 2-1:
DS70590B-page 18
MRF49XA
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
Note 1:
TXRXFIFO
DQDO
R-0
R-0
2:
3:
4:
5:
Control
All register commands begin with logic ‘1’ and only the STATUS register read command begins with logic ‘0’.
This bit is multiplexed for Transmit or Receive mode.
See the FFBC bits (FIFORSTREG<3:0>) in Register 2-10.
To get accurate values, the AFC should be disabled during the read by clearing the FOFEN bit
(AFCCREG<0>). The AFC offset value (OFFSB bits in the status word) is represented as a two’s
complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by
the current PLL frequency step from CFSREG (FREQB<11:0>).
This bit is cleared after STSREG is read.
TXRXFIFO: Transmit Register or Receive FIFO bit
Transmit mode: Transmit Register Ready bit
Indicates whether the transmit register is ready to receive the next byte for transmission.
1 = Ready
0 = Not ready
Receive mode: Receive FIFO Fill (Interrupt) bit
Indicates whether the RX FIFO has reached the preprogrammed limit.
1 = Reached the preprogrammed limit
0 = Programming limit has not been reached
POR: Power-on Reset bit
1 = POR has occurred
0 = POR has not occured
TXOWRXOF: Transmit Overwrite Receive Overflow bit
Transmit mode: Transmit Register Underrun or Overwrite bit
1 = Underrun or overwrite
0 = Operating normally
Receive mode: Receive FIFO Overflow bit
1 = FIFO overflow
0 = Operating normally
WUTINT: Wake-up Timer (Interrupt) Overflow bit
1 = Timer overflow has occurred
0 = Operating normally
LCEXINT: Logic Change on External Interrupt bit
Indicates a high-to-low logic level change on external interrupt pin (INT/DIO).
1 = High-to-low transition has occurred
0 = High-to-low transition has not occured
CLKRL
(
POR
Command
R-0
R-0
STSREG: STATUS READ REGISTER (POR: 0x0000)
(5)
r = reserved bit
W = Writable bit
‘1’ = Bit is set
TXOWRXOF
AFCCT
)
(5)
R-0
R-0
Register Details
(5)
(5)
WUTINT
OFFSV
(5)
R-0
R-0
Preliminary
(5)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
LCEXINT
(2,3)
R-0
R-0
LBTD
R-0
R-0
OFFSB<3:0>
(1)
© 2009 Microchip Technology Inc.
x = Bit is unknown
FIFOEM
(5)
R-0
R-0
ATRSSI
R-0
R-0
bit 8
bit 0