5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 100

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

6–6
MAX V Device Handbook
IEEE 1532 Support
Jam Standard Test and Programming Language
Programming Sequence
f
f
The JTAG circuitry and ISP instruction set in MAX V devices are compliant to the
IEEE-1532-2002 programming specification. This provides industry-standard
hardware and software for in-system programming among multiple vendor
programmable logic devices (PLDs) in a JTAG chain.
For more information about MAX V 1532 Boundary-Scan Description Language
(.bsd) files, refer to the
You can use the Jam STAPL to program MAX V devices with in-circuit testers, PCs, or
embedded processors. The Jam byte code is also supported for MAX V devices. These
software programming protocols provide a compact embedded solution for
programming MAX V devices.
For more information, refer to
Device
During in-system programming, 1532 instructions, addresses, and data are shifted
into the MAX V device through the TDI input pin. Data is shifted out through the TDO
output pin and compared with the expected data.
To program a pattern into the device, follow these steps:
1. Enter ISP—The enter ISP stage ensures that the I/O pins transition smoothly from
2. Check ID—The silicon ID is checked before any Program or Verify process. The
3. Sector Erase—Erasing the device in-system involves shifting in the instruction to
4. Program—Programming the device in-system involves shifting in the address,
5. Verify—Verifying a MAX V device in-system involves shifting in addresses,
6. Exit ISP—An exit ISP stage ensures that the I/O pins transition smoothly from ISP
user mode to ISP mode.
time required to read this silicon ID is relatively small compared to the overall
programming time.
erase the device and applying an erase pulse or pulses. The erase pulse is
automatically generated internally by waiting in the run, test, or idle state for the
specified erase pulse time of 500 ms for the CFM block and 500 ms for each sector
of the user flash memory (UFM) block.
data, and program instruction and generating the program pulse to program the
flash cells. The program pulse is automatically generated internally by waiting in
the run/test/idle state for the specified program pulse time of 75 µs. This process
is repeated for each address in the CFM and UFM blocks.
applying the verify instruction to generate the read pulse, and shifting out the data
for comparison. This process is repeated for each CFM and UFM address.
mode to user mode.
Programming.
IEEE 1532 BSDL Files
AN 425: Using Command-Line Jam STAPL Solution for
Chapter 6: JTAG and In-System Programmability in MAX V Devices
page of the Altera website.
December 2010 Altera Corporation
In-System Programmability