5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 159

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
I/O Voltage Support in the JTAG Chain
I/O Voltage Support in the JTAG Chain
December 2010 Altera Corporation
USERCODE Instruction Mode
CLAMP Instruction Mode
HIGHZ Instruction Mode
Use USERCODE instruction mode to examine the user electronic signature (UES) within
the devices along an IEEE Std. 1149.1 chain. When you select this instruction, the
device identification register is connected between the TDI and TDO ports. The user-
defined UES shifts into the device ID register in parallel from the 32-bit USERCODE
register. The UES then shifts out through the device ID register. The USERCODE
information is only available after the device is successfully configured.
Non-volatile USERCODE data is written to the configuration flash memory (CFM) block
and then written to the SRAM at power up. The USERCODE instruction reads the data
values from the SRAM. When you use real-time ISP to update the CFM block and
write new USERCODE data, executing the USERCODE instruction returns the USERCODE of
the current running design (stored in the SRAM), not the new USERCODE data. The
USERCODE of the new design (stored in the CFM) can only be read back correctly if a
power cycle or forced SRAM download has transpired after the real-time ISP update.
In the Quartus
to use the checksum value of a programming file as the JTAG user code. If selected,
the checksum is automatically loaded to the USERCODE register.
To enable the Auto Usercode feature, follow these steps:
1. On the Assignments menu, click Device.
2. In the Device dialog box, click Device and Pin Options and click the General tab.
3. Turn on Auto Usercode.
Use CLAMP instruction mode to allow the state of the signals driven from the pins to be
determined from the boundary-scan register while the bypass register is selected as
the serial path between the TDI and Tmv51008.fmDO ports. Data held in the boundary-
scan register completely defines the state of all signals driven from the output pins.
However, CLAMP instruction mode will not override the I/O weak pull-up resistor or
the I/O bus hold if you have any of them selected.
Use HIGHZ instruction mode to set all of the user I/O pins to an inactive drive state.
These pins are tri-stated until you execute a new JTAG instruction. When you select
this instruction, the bypass register is connected between the TDI and TDO ports. HIGHZ
instruction mode will not override the I/O weak pull-up resistor or I/O bus hold if
you have any of them selected.
There can be several different Altera or non-Altera devices in a JTAG chain. However,
you must pay attention to whether or not the chain contains devices with different
V
V
according to the V
CCIO
CCIO
of the device. For MAX V devices, the TDO pin drives out at the voltage level
levels. The TDO pin of a device drives out at the voltage level according to the
®
II software, there is an Auto Usercode feature where you can choose
CCIO
of I/O Bank 1. Although the devices may have different V
MAX V Device Handbook
CCIO
8–13