5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 111

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
UFM Operating Modes
January 2011 Altera Corporation
Read/Stream Read
The three control signals, PROGRAM, ERASE, and BUSY are not required during a read or
stream read operation. To perform a read operation, the address register must be
loaded with the reference address where the data is or is going to be located in the
UFM. The address register can be stopped from incrementing or shifting addresses
from ARDin by stopping the ARCLK clock pulse. DRSHFT must be asserted low at the next
rising edge of DRCLK to load the data from the UFM to the data register. To shift the bits
from the register, 16 clock pulses must be provided to read 16-bit wide data. You can
use DRCLK to control the read time or disable the data register by discontinuing the
DRCLK clock pulse.
The UFM block can also perform a stream read operation, using the address
increment feature to read continuously from the UFM. Stream read mode is started by
loading the base address into the address register. DRSHFT must then be asserted low at
the first rising edge of DRCLK to load data into the data register from the address
pointed to by the address register. DRSHFT will then assert high to shift out the 16-bit
wide data with the MSB out first.
during stream read mode.
Figure 7–5. UFM Read Waveforms
Figure 7–6. UFM Stream Read Waveforms
PROGRAM
PROGRAM
OSC_ENA
OSC_ENA
ARSHFT
DRSHFT
DRSHFT
ARSHFT
DRDout
DRDout
ARCLK
DRCLK
ERASE
DRCLK
ERASE
ARCLK
DRDin
ARDin
DRDin
ARDin
BUSY
BUSY
t
t
Figure 7–5
ASU
ADS
t
ACLK
9 Address Bits
9 Address Bits
shows the UFM control waveforms during read mode.
Figure 7–6
t
t
ADH
AH
t
DCO
t
Increment
DSS
Address
shows the UFM control waveforms
t
DCLK
16 Data Bits
16 Data Bits
t
DSH
MAX V Device Handbook
Increment
Address
7–9