5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 22

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

2–10
Figure 2–7. LE in Normal Mode
Note to
(1) This signal is only allowed in normal mode if the LE is after an adder/subtractor chain.
MAX V Device Handbook
addnsub (LAB Wide)
Figure
data1
data2
data3
cin (from cout
of previous LE)
data4
2–7:
(1)
Normal Mode
The normal mode is suitable for general logic applications and combinational
functions. In normal mode, four data inputs from the LAB local interconnect are
inputs to a four-input LUT as shown in
automatically selects the carry-in or the data3 signal as one of the inputs to the LUT.
Each LE can use LUT chain connections to drive its combinational output directly to
the next LE in the LAB. Asynchronous load data for the register comes from the data3
input of the LE. LEs in normal mode support packed registers.
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. A LE in dynamic arithmetic
mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first
two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the
other two LUTs generate carry outputs for the two chains of the carry-select circuitry.
As shown in
carry-in1 chain. The selected chain’s logic level in turn determines which parallel
sum is generated as a combinational or registered output. For example, when
implementing an adder, the sum output is the selection of two possible calculated
sums:
data1 + data2 + carry-in0
or
data1 + data2 + carry-in1
Register Feedback
Figure
4-Input
LUT
Register chain
connection
2–8, the LAB carry-in signal selects either the carry-in0 or
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
Figure
2–7. The Quartus II Compiler
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
Row, column, and
DirectLink routing
Row, column, and
DirectLink routing
Local routing
LUT chain
connection
Register
chain output
Logic Elements