5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 126

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–24
MAX V Device Handbook
The Quartus II software supports both the Base mode (uses 8-bit address and data)
and the Extended mode (uses 16-bit address and data). Base mode uses only UFM
sector 0 (2,048 bits), while Extended mode uses both UFM sector 0 and sector 1 (8,192
bits). There are only four pins in SPI: SI, SO, SCK, and nCS.
pins and functions.
Table 7–9. SPI Interface Signals
Data transmitted to the SI port of the slave device is sampled by the slave device at
the positive SCK clock. Data transmits from the slave device through SO at the negative
SCK clock edge. When nCS is asserted, it means the current device is being selected by
the master device from the other end of the SPI bus for service. When nCS is not
asserted, the SI and SCK ports should be blocked from receiving signals from the
master device, and SO should be in High Impedance state to avoid causing contention
on the shared SPI bus. All instructions, addresses, and data are transferred with the
MSB first and start with high-to-low nCS transition. The circuit diagram is shown in
Figure
Figure 7–20. Circuit Diagram for SPI Interface Read or Write Operations
SI
SO
SCK
nCS
Pin
7–20.
UFM Block
Serial Data Input
Serial Data Output
Serial Data Clock
Chip Select
Description
Receive data serially.
Transmit data serially.
The clock signal produced from the master device to
synchronize the data transfer.
Active low signal that enables the slave device to
receive or transfer data from the master device.
Eight-Bit Status Shift Register
Read, Write, and Erase
Address and Data Hub
Op-Code Decoder
Chapter 7: User Flash Memory in MAX V Devices
State Machine
Table 7–9
Function
January 2011 Altera Corporation
Software Support for UFM Block
describes the SPI
Control Logic
SPI Interface
SI SO SCK nCS