5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 138

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–36
Table 7–15. Parallel Interface Signals
MAX V Device Handbook
DI[15..0]
DO[15..0]
ADDR[8..0]
nREAD
nWRITE
nERASE
nBUSY
DATA_VALID
Pin
Parallel Interface
16-bit data Input
16-bit data Output
Address Register
READ Instruction Signal
WRITE Instruction Signal
ERASE Instruction Signal
BUSY Signal
Data Valid
This interface allows for parallel communication between the UFM block and outside
logic. After the READ request, WRITE request, or ERASE request is asserted (active low
assertion), the outside logic or device (such as a microcontroller) can continue its
operation while the data in the UFM is retrieved, written, or erased. During this time,
the nBUSY signal is driven “low” to indicate that it is not available to respond to any
further request. After the operation is complete, the nBUSY signal is brought back to
“high” to indicate that it is now available to service a new request. If it was the Read
request, the DATA_VALID is driven “high” to indicate that the data at the DO port is the
valid data from the last read address.
Asserting READ, WRITE, and ERASE at the same time is not allowed. Multiple requests
are ignored and nothing is read from, written to, or erased in the UFM block. There is
no support for sequential read and page write in the parallel interface. For both the
read only and the read/write modes of the parallel interface, OSC_ENA is always
asserted, enabling the internal oscillator.
functions.
Even though the ALTUFM megafunction allows you to select the address widths
range from 3 bits to 9 bits, the UFM block always expects a full 9 bits for the width of
the address register. Therefore, the ALTUFM megafunction will always pad the
remaining LSBs of the address register with '0's if the register width selected is less
than 9 bits. The address register will point to sector 0 if the address received at the
address register starts with a '0'. The address register will point to sector 1 if the
address received starts with a '1'.
Even though you can select an optional data register width of 3 to 16 bits using the
ALTUFM megafunction, the UFM block always expects full 16 bits width for the data
register. Reading from the data register always proceeds from MSB to LSB. The
ALTUFM megafunction always pads the remaining LSBs of the data register with 1s if
the user selects a data width of less than 16-bits.
Description
Receive 16-bit data in parallel. You can select an optional width of 3 to
16 bits using the ALTUFM megafunction.
Transmit 16-bit data in parallel. You can select an optional width of 3 to
16 bits using the ALTUFM megafunction.
Operation sequence refers to the data that is pointed to by the address
register. You can determine the address bus width using the ALTUFM
megafunction.
Initiates a read sequence.
Initiates a write sequence.
Initiates a SECTOR-ERASE sequence indicated by the MSB of the
ADDR[] port.
Driven low to notify that it is not available to respond to any further
request.
Driven high to indicate that the data at the DO port is the valid data from
the last read address for read request.
Table 7–15
Chapter 7: User Flash Memory in MAX V Devices
Function
lists the parallel interface pins and
January 2011 Altera Corporation
Software Support for UFM Block