5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 149

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–2. IEEE Std. 1149.1 Circuitry
IEEE Std. 1149.1 Boundary-Scan Register
December 2010 Altera Corporation
Note to
(1) For the boundary-scan register length in MAX V devices, refer to the
TMS
TCK
Figure
TDI
8–2:
Controller
TAP
Figure 8–2
The TAP controller controls the IEEE Std. 1149.1 boundary-scan testing, as described
in
operate the TAP controller and the TDI and TDO pins provide the serial path for the
data registers. The TDI pin also provides data to the instruction register, which then
generates the control logic for the data registers.
The boundary-scan register is a large serial shift register that uses the TDI pin as an
input and the TDO pin as an output. The boundary-scan register consists of 3-bit
peripheral elements that are associated with the I/O pins of the MAX V devices. You
can use the boundary-scan register to test the external pin connections or to capture
internal data.
“IEEE Std. 1149.1 BST Operation Control” on page
UPDATEDR
UPDATEIR
CLOCKDR
CLOCKIR
SHIFTDR
SHIFTIR
shows a functional model of the IEEE Std. 1149.1 circuitry.
Data Registers
Instruction Register
Bypass Register
Boundary-Scan Register (1)
Device ID Register
ISP Registers
Instruction Decode
a
JTAG and In-System Programmability in MAX V Devices
8–6. The TMS and TCK pins
MAX V Device Handbook
chapter.
TDO
8–3