5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 20

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

2–8
Logic Elements
Figure 2–6. LE for MAX V Devices
MAX V Device Handbook
Reset (DEV_CLRn)
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
data1
data2
data3
data4
addnsub
The smallest unit of logic in the MAX V architecture, the LE, is compact and provides
advanced features with efficient logic utilization. Each LE contains a four-input LUT,
which is a function generator that can implement any function of four variables. In
addition, each LE contains a programmable register and carry chain with carry-select
capability. A single LE also supports dynamic single-bit addition or subtraction mode
that is selected by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and DirectLink
interconnects as shown in
You can configure each LE’s programmable register for D, T, JK, or SR operation. Each
register has data, true asynchronous load data, clock, clock enable, clear, and
asynchronous load/preset inputs. Global signals, general purpose I/O (GPIO) pins,
or any LE can drive the register’s clock and clear control signals. Either GPIO pins or
LEs can drive the clock enable, preset, asynchronous load, and asynchronous data.
The asynchronous load data input comes from the data3 input of the LE. For
combinational functions, the LUT output bypasses the register and drives directly to
the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output can drive these three outputs independently. Two LE outputs
drive either a column or row and DirectLink routing connections while one output
drives the local interconnect resources. This configuration allows the LUT to drive one
output while the register drives another output. This register packing feature
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock and
LAB Carry-In
Select
Carry-In1
Carry-In0
Look-Up
Table
(LUT)
Chain
Carry
Register chain
routing from
previous LE
Figure
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
2–6.
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
Packed
Register Select
ADATA
D
ENA
PRN/ALD
CLRN
Register
Feedback
Q
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
Programmable
Register
LUT chain
routing to next LE
Row, column,
and DirectLink
routing
Row, column,
and DirectLink
routing
Local routing
Register chain
output
Logic Elements