5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 158

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

8–12
Figure 8–11. EXTEST Shift Data Register Waveforms
Figure 8–12. BYPASS Shift Data Register Waveforms
MAX V Device Handbook
TAP_STATE
TMS
TDO
TCK
TAP_STATE
TDI
TMS
TDO
TCK
BYPASS Instruction Mode
IDCODE Instruction Mode
TDI
SHIFT_IR
SHIFT_IR
f
Instruction Code
Figure 8–11
instruction code for EXTEST is different. The data shifted out of TDO consists of the data
that was present in the capture registers after the capture phase. New test data shifted
into the TDI pin appears at the TDO pin after being clocked through the entire
boundary-scan register.
You can activate BYPASS instruction mode with an instruction code made up of only
ones.
controller is in the SHIFT_DR state. In this state, data signals are clocked into the bypass
register from TDI on the rising edge of TCK and out of TDO on the falling edge of the
same clock pulse.
Use IDCODE instruction mode to identify the devices in an IEEE Std. 1149.1 chain.
When you select IDCODE, the device identification register loads with the 32-bit
vendor-defined identification code. The device ID register is connected between the
TDI and TDO ports and the device IDCODE is shifted out.
IDCODE instruction mode for MAX V devices are listed in the
Programmability in MAX V Devices
Instruction Code
Figure 8–12
EXIT1_IR
resembles the SAMPLE/PRELOAD waveform diagram, except that the
UPDATE_IR
EXIT1_IR
SELECT_DR_SCAN
UPDATE_IR
shows how scan data passes through a device after the TAP
SELECT_DR_SCAN
CAPTURE_DR
CAPTURE_DR
Bit 1
chapter.
Bit 2
Bit 1
Data stored in
boundary- scan
register is shifted
out of TDO.
SHIFT_DR
Data shifted into TDI on
the rising edge of TCK is
shifted out of TDO on the
falling edge of the same
TCK pulse.
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
Bit 3
Bit 2
Bit n
After boundry-scan
register data has been
shifted out, data
entered into TDI will
shift out of TDO.
IEEE Std. 1149.1 BST Operation Control
SHIFT_DR
December 2010 Altera Corporation
JTAG and In-System
EXIT1_DR
EXIT1_DR
UPDATE_DR
UPDATE_DR