5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 99

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 6: JTAG and In-System Programmability in MAX V Devices
In-System Programmability
Figure 6–1. PFL for MAX V Devices
In-System Programmability
December 2010 Altera Corporation
Notes to
(1) This block is implemented in logic elements (LEs).
(2) This function is supported in the Quartus II software.
Figure
6–1:
Memory Device
Flash
DQ[7..0]
A[20..0]
Figure 6–1
You can program MAX V devices in-system through the industry standard 4-pin
IEEE Std. 1149.1 interface. ISP offers quick and efficient iterations during design
development and debugging cycles. The flash-based SRAM configuration elements
configure the logic, circuitry, and interconnects in the MAX V architecture. Each time
the device is powered up, the configuration data is loaded into the SRAM elements.
The process of loading the SRAM data is called configuration. The on-chip
configuration flash memory (CFM) block stores the configuration data of the SRAM
element. The CFM block stores the configuration pattern of your design in a
reprogrammable flash array. During ISP, the MAX V JTAG and ISP circuitry programs
the design pattern into the non-volatile flash array of the CFM block.
The MAX V JTAG and ISP controller internally generate the high programming
voltages required to program the CFM cells, allowing in-system programming with
any of the recommended operating external voltage supplies. You can configure the
ISP anytime after you have fully powered V
has completed the configuration power-up time. By default, during in-system
programming, the I/O pins are tri-stated and weakly pulled-up to V
eliminate board conflicts. The in-system programming clamp and real-time ISP
feature allow user control of the I/O state or behavior during ISP.
For more information, refer to
“Real-Time ISP” on page
These devices also offer an ISP_DONE bit that provides safe operation if in-system
programming is interrupted. This ISP_DONE bit, which is the last bit programmed,
prevents all I/O pins from driving until the bit is programmed.
RY/BY
WE
OE
CE
TMS
TDO
TCK
TDI
shows how you can use the MAX V JTAG block as a PFL.
RUNIDLE_U
UPDATE_U
CLKDR_U
USER1_U
SHIFT_U
TDO_U
TMS_U
TCK_U
TDI_U
6–8.
“In-System Programming Clamp” on page 6–7
MAX V Device
Configuration
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
(1), (2)
Logic
PFL
CCINT
and all V
CCIO
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
banks, and the device
Altera FPGA
MAX V Device Handbook
CCIO
banks to
and
6–5