5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 41

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 2: MAX V Architecture
I/O Structure
December 2010 Altera Corporation
I/O Standards and Banks
Figure 2–21
Figure 2–21. Column I/O Block Connection to the Interconnect
Note to
(1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and
Table 2–4
Table 2–4. MAX V I/O Standards (Part 1 of 2)
Local Interconnect
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
one data_in input.
I/O Block
Figure
LAB Local
Interconnect
I/O Standard
lists the I/O standards supported by MAX V devices.
R4 Interconnects
2–21:
shows how a column I/O block connects to the logic array.
data_out
C4 Interconnects
[3..0]
LAB
4
[3..0]
OE
4
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Column I/O Block
Type
Interconnect
LAB Local
Interconnect
fast_out
Fast I/O
[3..0]
Path
LAB
4
LAB Column
Clock [3..0]
(Note 1)
Output Supply Voltage (V
4
data_in
[3..0]
C4 Interconnects
MAX V Device Handbook
3.3
2.5
1.8
1.5
1.2
(V)
Column I/O
Block Contains
Up To 4 IOEs
LAB Local
Interconnect
LAB
CCIO
2–29
)