5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 143

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Creating Memory Content File
Figure 7–38. Memory Map for 2-Kbit Memory Initialization
January 2011 Altera Corporation
2-Kbit ALTUFM_I2C Megafunction
Upper Half – Addresses
Lower Half – Addresses
Logical Memory Contents
80h to FFh
00h to 7Fh
Memory Map for 2-Kbit Memory Initialization
Figure 7–38
of 2 Kbits of memory. The ALTUFM_I2C megafunction byte address location of 00h to
7Fh is mapped to the UFM block address location of 000h to 07Fh. The ALTUFM_I2C
megafunction byte address location of 80h to FFh is mapped to the UFM block address
location of 180h to 1FFh. Altera recommends that you pad the unused address location
of the UFM block with all 1s.
FFh
shows the memory map initialization for the ALTUFM_I2C megafunction
80h
00h
7Fh
1FFh
180h
17Fh
07Fh
080h
000h
the actual data and address size for the UFM block
memory maps to 1FFh in the MIF/HEX file, and all
logical memory maps to 07Fh in the MIF/HEX file,
address 000h in the MIF/HEX file. Address 7Fh in
address 180h in the MIF/HEX file. FFh in logical
MIF or HEX File Contents – to represent
and all data in between follows the order in the
the MIF/HEX file contents should be set to
Address 80h in logical memory maps to
Address 00h in logical memory maps to
data in between follows the order in the
This section of the UFM is unused –
all '1' for addresses 080h to 17Fh
logical memory
logical memory
MAX V Device Handbook
7–41