5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 120

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–18
MAX V Device Handbook
The ALTUFM_I2C megafunction supports four different erase operation methods
shown on page 4 of the ALTUFM MegaWizard Plug-In Manager:
■
■
■
■
These erase options only work as described if that particular option is selected in the
MegaWizard Plug-In Manager before compiling the design files and programming
the device. Only one option can be selected for the ALTUFM_I2C megafunction.
Each erase option is discussed in more detail in the following sections.
Full Erase (Device Slave Address Triggered)
The full erase option uses the A
between an erase or read/write operation. This slave operation decoding occurs when
the master transfers the slave address to the slave after generating the start condition.
If the A
the four remaining MSBs match the rest of the slave addresses, then the Full Erase
operation is selected. If the A
to the UFM match its unique slave address setting, the read/write operation is
selected and functions as expected. As a result, this erase option utilizes two slave
addresses on the bus reserving A
of the UFM block will be erased when the Full Erase operation is executed. This
operation requires acknowledge polling. The internal UFM erase function only begins
after the master generates a stop condition.
triggered by using the slave address.
If the memory is write-protected (WP = 1), the slave does not acknowledge the erase
trigger slave address (A
then send a stop condition to terminate the transfer. The full erase operation will not
be executed.
Figure 7–13. Full Erase Sequence Triggered Using the Slave Address
Full Erase (Device Slave Address Triggered)
Sector Erase (Byte Address Triggered)
Sector Erase (A
No Erase
2
, A
1
, and A
2
0
S – Start Condition
P – Stop Condition
A – Acknowledge
Triggered)
slave address bits transmitted to the UFM slave equals 111 and
S
6
, A
Slave Address
A
5
, A
6
6
A
, A
5
A
4
2
, A
4
, A
5
A
6
, A
, A
3
111
3
1
, 1, 1, 1) sent by the master. The master should
4
, A
, A
5
, A
'0' (write)
0
3
bits of the slave address to distinguish
4
A
R/W
, A
2
, A
Figure 7–13
3
, 1, 1, 1 as the erase trigger. Both sectors
1
A
, and A
Chapter 7: User Flash Memory in MAX V Devices
P
From Master to Slave
From Slave to Master
0
slave address bits transmitted
shows the full erase sequence
January 2011 Altera Corporation
Software Support for UFM Block