5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 42

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

2–30
MAX V Device Handbook
Table 2–4. MAX V I/O Standards (Part 2 of 2)
The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices support two I/O banks,
as shown in
and RSDS standards shown in
devices and banks.
Figure 2–22. I/O Banks for 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z Devices
Notes to
(1)
(2)
(3) This I/O standard is not supported in Bank 1.
(4) Emulated LVDS output using a three resistor network (LVDS_E_3R).
(5) Emulated RSDS output using a three resistor network (RSDS_E_3R).
3.3-V PCI
LVDS
RSDS
Notes to
(1) The 3.3-V PCI compliant I/O is supported in Bank 3 of the 5M1270Z and 5M2210Z devices.
(2) MAX V devices only support emulated LVDS output using a three resistor network (LVDS_E_3R).
(3) MAX V devices only support emulated RSDS output using a three resistor network (RSDS_E_3R).
Figure 2–22
Figure 2–22
I/O Bank 1
(2)
(3)
Figure
Table
I/O Standard
(1)
Figure
2–22:
is a top view of the silicon die.
is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.
2–4:
2–22. Each of these banks support all the LVTTL, LVCMOS, LVDS,
Table
All I/O Banks Support
3.3-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS,
1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS,
1.2-V
LVDS (4)
RSDS (5)
2–4. PCI compliant I/O is not supported in these
Single-ended
Differential
Differential
LVCMOS (3),
Type
,
Output Supply Voltage (V
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
3.3
2.5
2.5
(V)
(Note
I/O Bank 2
I/O Structure
1),
CCIO
(2)
)