5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 135

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
January 2011 Altera Corporation
RDSR (Read Status Register)
The content of the status register can be read by issuing RDSR. After RDSR is received,
the interface outputs the content of the status register through the SO port. Although
the four most significant bits (Bit 7 to Bit 4) do not hold valuable information, all eight
bits in the status register will output through the SO port. This allows future
compatibility when Bit 7 to Bit 4 have new meaning in the status register. During the
internal program cycle in the UFM, RDSR is the only valid opcode recognized by the
interface (therefore, the status register can be read at any time), and nRDY is the only
valid status bit. Other status bits are frozen and remain unchanged until the internal
program cycle is ended. RDSR is issued through the following sequence, as shown in
Figure
1. nCS is pulled low.
2. Opcode 00000101 is transmitted into the interface.
3. SI ignores incoming signals; SO outputs the content of the status register, Bit 7 first
4. If nCS is kept low, repeat step 3.
5. nCS is pulled back to high to terminate the transmission.
Figure 7–30. RDSR Operation Sequence
and Bit 0 last.
7–30:
SCK
nCS
SI
SO
High Impedance
MSB
0
1
Instruction
2
8-bit
05
3
H
4
5 6 7
8
MSB
MSB
Status Register Out
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MSB
MAX V Device Handbook
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