5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 96

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

6–2
Table 6–1. JTAG Instructions for MAX V Devices (Part 2 of 2)
MAX V Device Handbook
IDCODE
HIGHZ
CLAMP
USER0
USER1
IEEE 1532
instructions
Note to
(1) HIGHZ, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features.
JTAG Instruction
Table
(1)
(1)
6–1:
w
You must not issue unsupported JTAG instructions to the MAX V device because this
may put the device into an unknown state, requiring a power cycle to recover device
operation.
For the instruction codes
of the IEEE 1532
instructions, refer to the
IEEE 1532 BSDL Files
page of the Altera
website.
Instruction Code
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 1100
00 0000 1110
Selects the IDCODE register and places it between the TDI and TDO
pins, allowing you to shift the IDCODE register out of the TDO pin
serially.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through target
devices to adjacent devices if the device is operating in normal mode
and tri-stating all the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through target
devices to adjacent devices during normal device operation and
holding I/O pins to a state defined by the data in the boundary-scan
register.
Allows you to define the scan chain between the TDI and TDO pins in
the MAX V logic array. Use this instruction for custom logic and
JTAG interfaces.
Allows you to define the scan chain between the TDI and TDO pins in
the MAX V logic array. Use this instruction for custom logic and
JTAG interfaces.
IEEE 1532 in-system concurrent (ISC) instructions used if
programming a MAX V device through the JTAG port.
Chapter 6: JTAG and In-System Programmability in MAX V Devices
Description
IEEE Std. 1149.1 Boundary-Scan Support
December 2010 Altera Corporation