5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 144

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–42
Figure 7–39. Memory Map for 4-Kbit Memory Initialization
Figure 7–40. Memory Map for 8-Kbit Memory Initialization
MAX V Device Handbook
8-Kbit ALTUFM_I2C Megafunction
4-Kbit ALTUFM_I2C Megafunction
Mid-Upper Quarter Addresses
Mid-Lower Quarter Addresses
Upper Half – Addresses
Lower Half – Addresses
Logical Memory Contents
Upper Quarter Addresses
Lower Quarter Addresses
Logical Memory Contents
100h to 1FFh
00h to FFh
Memory Map for 4-Kbit Memory Initialization
Figure 7–39
of 4-Kbit memory. The ALTUFM_I2C megafunction byte address location of 00h to
FFh is mapped to the UFM block address location of 000h to 0FFh. The ALTUFM_I2C
megafunction byte address location of 100h to 1FFh is mapped to the UFM block
address location of 100h to 1FFh.
Memory Map for 8-Kbit Memory Initialization
Figure 7–40
of 8-Kbit memory. The ALTUFM_I2C megafunction of 8-Kbit memory fully utilizes all
the memory locations in the UFM block.
300h to 3FFh
200h to 2FFh
100h to 1FFh
000h to 0FFh
shows the memory map initialization for the ALTUFM_I2C megafunction
shows the memory map initialization for the ALTUFM_I2C megafunction
3FFh
2FFh
1FFh
0FFh
300h
200h
100h
000h
1FFh
100h
00h
FFh
100h
0FFh
000h
1FFh
1FFh
100h
0FFh
000h
The upper quarter of
logical memory maps
to the upper byte of
sector 1. Address 300h
in logical memory
maps to address 100h
in physical memory
and all addresses
follow the order in
logical memory.
The mid-lower quarter of
logical memory maps
to the lower byte of
sector 0. Address 100h
in logical memory
maps to address 000h
in physical memory
and all addresses
follow the order in
logical memory.
Upper 8-bit (byte)
actual data and address size for the UFM Block
the data and address size for the UFM block
memory maps to 1FFh in the MIF/HEX file, and all
memory maps to 0FFh in the MIF/HEX file, and all
100h in the MIF/HEX file. Address 1FFh in logical
MIF or HEX File Contents - to represent the
000h in the MIF/HEX file. Address FFh in logical
MIF or HEX File Contents – to represent
Address 100h in logical memory maps to
Address 00h in logical memory maps to
data in between follows the order in the
data in between follows the order in the
16-bit data in UFM
Chapter 7: User Flash Memory in MAX V Devices
logical memory
logical memory
The mid-upper quarter of
logical memory maps
to the lower byte of
sector 1. Address 200h
in logical memory
maps to address 100h
in physical memory
and all addresses
follow the order in
logical memory.
The lower quarter of
logical memory maps
to the lower byte of
sector 0. Address 000h
in logical memory
maps to address 000h
in physical memory
and all addresses
follow the order in
logical memory.
Lower 8-bit (byte)
January 2011 Altera Corporation
Creating Memory Content File