5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 113

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
UFM Operating Modes
January 2011 Altera Corporation
Erase
1
The ERASE signal initiates an erase sequence to erase one sector of the UFM. The data
register is not needed to perform an erase sequence. To indicate the sector of the UFM
to be erased, the MSB of the address register should be loaded with 0 to erase UFM
sector 0, or 1 to erase UFM sector 1
ERASE signal, the memory sector indicated by the MSB of the address register will be
erased. The BUSY signal is asserted until the erase sequence is completed. The address
register should not be modified until the BUSY signal is de-asserted to prevent the flash
content from being corrupted. This ERASE signal is ignored when the BUSY signal is
asserted.
When the UFM sector is erased, it has 16-bit locations all filled with FFFF. Each UFM
storage bit can be programmed only once between erase sequences. You can write to
any word up to two times providing the second programming attempt at that location
only adds 0s. 1s are mask bits for your input word that cannot overwrite 0s in the
flash array. New 1s in the location can only be achieved by an erase. Therefore, it is
possible for you to perform byte writes because the UFM array is 16 bits for each
location.
Figure 7–8. UFM Erase Waveforms
Figure 7–8
PROGRAM
OSC_ENA
DRSHFT
ARSHFT
DRDout
DRCLK
ERASE
ARCLK
ARDin
DRDin
BUSY
illustrates the UFM waveforms during erase mode.
t
t
ASU
ADS
t
ACLK
(Figure 7–2 on page
9 Address Bits
t
ADH
t
AH
t
EB
t
OSCS
7–5). On a rising edge of the
t
EPMX
t
OSCH
t
MAX V Device Handbook
BE
7–11