5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 95

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

MV51006-1.0
IEEE Std. 1149.1 Boundary-Scan Support
Table 6–1. JTAG Instructions for MAX V Devices (Part 1 of 2)
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MAX V Device Handbook
December 2010
December 2010
MV51006-1.0
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
JTAG Instruction
(1)
This chapter describes the IEEE Standard 1149.1 JTAG BST circuitry that is supported
in MAX
multiple devices in a minimum time with the IEEE Standard 1532 in-system
programmability (ISP). This chapter also describes the programming sequence, types
of programming with the Quartus
security.
This chapter includes the following sections:
■
■
All MAX V devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-2001 specification. You can only perform JTAG boundary-scan
testing after you have fully powered the V
amount of configuration time (t
MAX V devices can use the JTAG port with either the Quartus II software or
hardware with Programmer Object File (.pof), Jam
Language (STAPL) Format File (.jam), or Jam Byte Code Files (.jbc).
JTAG pins support 1.5-V, 1.8-V, 2.5-V, and 3.3-V I/O standards. The V
where it is located determines the supported voltage level and standard. The
dedicated JTAG pins reside in Bank 1 of all MAX V devices.
Table 6–1
“IEEE Std. 1149.1 Boundary-Scan Support” on page 6–1
“In-System Programmability” on page 6–5
Instruction Code
®
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
V devices and how you can enable concurrent in-system programming of
lists the JTAG instructions supported in MAX V devices.
6. JTAG and In-System Programmability
Allows you to capture and examine a snapshot of signals at the
device pins if the device is operating in normal mode. Permits an
initial data pattern to be an output at the device pins.
Allows you to test the external circuitry and board-level
interconnects by forcing a test pattern at the output pins and
capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the boundary-scan test (BST) data to pass
synchronously through target devices to adjacent devices during
normal device operation.
Selects the 32-bit USERCODE register and places it between the TDI
and TDO pins, allowing you to shift the USERCODE register out of the
TDO pin serially. If you do not specify the USERCODE in the Quartus II
software, the 32-bit USERCODE register defaults to all 1’s.
CONFIG
®
II software or external hardware, and design
) have passed. For in-system programming,
CCINT
and all V
™
Description
Standard Test and Programming
CCIO
in MAX V Devices
banks and a certain
CCIO
of the bank
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