5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 106

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–4
Table 7–4. UFM Interface Signals (Part 2 of 2)
MAX V Device Handbook
PROGRAM
ERASE
OSC_ENA
DRDout
BUSY
OSC
RTP_BUSY
Port Name
f
Port Type
Output
Output
Output
Output
Input
Input
Input
For more information about the interaction between the UFM block and the logic
array of MAX V devices, refer to the
Signal that initiates a program sequence. On the rising edge, the data in the data register is
written to the address pointed to by the address register. The BUSY signal asserts until the
program sequence is completed.
Signal that initiates an erase sequence. On a rising edge, the memory sector indicated by
the MSB of the address register is erased. The BUSY signal asserts until the erase sequence
is completed.
This signal turns on the internal oscillator in the UFM block. It is required when the OSC
output is used, but optional otherwise. If OSC_ENA is driven high, the internal oscillator is
enabled and the OSC output will toggle. If OSC_ENA is driven low, the internal oscillator is
disabled and the OSC output drives constant high.
Serial output of the data register. Each time the DRCLK signal is applied, a new value is
available. The DRDout data depends on the DRSHFT signal. When the DRSHFT signal is high,
DRDout contains the new value that is shifted into the MSB of the data register. If DRSHFT is
low, DRDout contains the MSB of the memory location read into the data register.
Signal that indicates when the memory is BUSY performing a PROGRAM or ERASE
instruction. When it is high, the address and data register should not be clocked. The new
PROGRAM or ERASE instruction is not executed until the BUSY signal is deasserted.
Output of the internal oscillator. It can be used to generate a clock to control user logic with
the UFM. It requires an OSC_ENA input to produce an output.
This output signal is optional and only needed if the real-time ISP feature is used. The signal
is asserted high during real-time ISP and stays in the RUN_STATE for 500 ms before
initiating real-time ISP to allow for the final read/erase/write operation. No read, write,
erase, or address and data shift operations are allowed to be issued after the RTP_BUSY
signal goes high. The data and address registers do not retain the contents of the last read
or write operation for the UFM block during real-time ISP.
MAX V Device Architecture
Description
Chapter 7: User Flash Memory in MAX V Devices
January 2011 Altera Corporation
chapter.
UFM Functional Description