DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 140

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: BIST Enable (BISTE). If this bit is set the device performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the device after completion of BIST test
before normal dataflow can begin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: BIST DONE (BISTDN). If this bit is set to 1, the device has completed the BIST Test initiated by BISTE. The
pass-fail result is available in BISTPF.
Bit 0: BIST PassFail (BISTPF). This bit is equal to 0 after the device performs BIST testing on the SDRAM and
the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and the
BIST DN bit is set. If set this bit can only be cleared by resetting the device.
Register Name:
Register Description:
Register Address:
Bits 5 and 4: Frame Delay (FD[1:0]). Configures the delay that the frames are stored in the differential delay
compensation RAM before being sent to the HDLC. The default value is 0 for a frame delay of 2 frames. A value of
“01” = 3 frames, “10” = 4 frames, and “11” = 5 frames.
Bit 3: Local Machine Reset 3 (LSRMC3). Setting this bit to 1 resets the local IMUX state machine for link 4. Clear
for normal operation.
Bit 2: Local Machine Reset 2 (LSRMC2). Setting this bit to 1 resets the local IMUX state machine for link 3. Clear
for normal operation.
Bit 1: Local Machine Reset 1 (LSRMC1). Setting this bit to 1 resets the local IMUX state machine for link 2. Clear
for normal operation.
Bit 0: Local Machine Reset 0 (LSRMC0). Setting this bit to 1 resets the local IMUX state machine for link 1. Clear
for normal operation.
Bit #
Name
Default
—
—
—
0
7
0
7
0
7
GL.LSMRRFD
Global Local Synchronization Machine Reset and Receive Frame Delay
38h
—
—
—
6
0
6
0
6
GL.BISTEN
BIST Enable
20h
GL.BISTPF
BIST PassFail
21h
FD1
—
—
5
0
5
0
5
0
140 of 335
FD0
—
—
4
0
0
0
4
4
LSMRC3
—
—
3
0
3
0
3
0
LSMRC2
—
—
2
0
2
0
2
0
LSMRC1
BISTDN
—
1
0
1
0
1
0
LSMRC0
BISTPF
BISTE
0
0
0
0
0
0