DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 202

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Software Signaling Insertion Enable for Channels 24 to 17 (CH24 to CH17). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 1: Software Signaling Insertion Enable for LCAW and Channels 22 to 16 (CH22 to CH16). These
bits determine which channels are to have signaling inserted from the transmit signaling registers.
Bit 0: Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from
the lower 4 bits of the TS1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Software Signaling Insertion Enable for Channels 30 to 23 (CH30 to CH23). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
0 = do not source the lower CAS align/alarm bits from the TR.TS1 register
1 = source the lower CAS alarm align/bits from the TR.TS1 register
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
CH24
CH22
CH30
7
0
7
0
7
0
TR.SSIE3 (T1 Mode)
Software Signaling-Insertion Enable 3
0Ah
TR.SSIE3 (E1 Mode)
Software Signaling Insertion Enable 3
0Ah
TR.SSIE4
Software Signaling Insertion Enable 4
0Bh
CH23
CH21
CH29
6
0
6
0
6
0
CH22
CH20
CH28
5
0
5
0
5
0
202 of 335
CH21
CH19
CH27
4
0
4
0
4
0
CH26
CH20
CH18
3
0
3
0
3
0
CH19
CH17
CH25
2
0
2
0
2
0
CH18
CH16
CH24
1
0
1
0
1
0
LCAW
CH17
CH23
0
0
0
0
0
0