DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 219

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 4: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 3: Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.
Bits 2 to 0: Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read
of the receive FIFO.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.
Bit 2: HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
Bit 1: HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.
Bit 0: HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
PS2
0
0
0
0
1
PS1
0
0
1
1
0
—
—
7
0
7
0
PS0
0
1
0
1
0
TR.INFO5, TR.INFO6
HDLC #1 Information Register
HDLC #2 Information Register
2Eh, 2Fh
TR.INFO4
HDLC Event Information Register #4
2Dh
In Progress
Packet OK: Packet ended with correct CRC codeword
CRC Error: A closing flag was detected, preceded by a corrupt CRC
codeword
Abort: Packet ended because an abort signal was detected (seven
or more 1s in a row).
Overrun: HDLC controller terminated reception of packet because
receive FIFO is full.
—
—
6
0
6
0
TEMPTY
—
5
0
5
0
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TFULL
—
Packet Status
4
0
4
0
REMPTY
H2UDR
3
0
3
0
H2OBT
PS2
2
0
2
0
H1UDR
PS1
1
0
1
0
H1OBT
PS0
0
0
0
0