DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 40

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
9.3 Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Apply 3.3V supplies, then apply 1.8V supplies.
STEP 2: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 9.2.
Clear all reset bits. Allow 5ms for the reset recovery.
STEP 3: Reset the integrated T1/E1/J1 Transceivers through hardware using the TSTRST pin or through software
using the SFTRST function in the master mode register.
STEP 4: The LIRST (TR.LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. Allow 40ms for
the reset recovery.
STEP 5: Check the Ethernet Mapper Device ID in the
GL.IDRL
and
GL.IDRH
registers.
STEP 6: Check the T1/E1/J1 Transceiver Device ID in the TR.IDR register.
STEP 7: Configure the system clocks. Allow the clock system to properly adjust.
STEP 8: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 9: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 10: Setup connection in the GL.CON1 register.
STEP 11: Configure the Serial Port register space as needed.
STEP 12: Configure the Ethernet Port register space as needed.
STEP 13: Configure the Ethernet MAC indirect registers as needed.
STEP 14: Configure the T1/E1/J1 Framer as needed.
STEP 15: Configure the T1/E1/J1 LIU as needed.
STEP 16: Configure the external Ethernet PHY through the MDIO interface.
STEP 17: Enable the elastic store on each of the integrated T1/E1 transceivers.
STEP 18: Configure each T1/E1 transceiver’s position on the IBO bus through TR.IBOC.
STEP 19: Choose a T1/E1 transceiver to as the 8kHz frame sync source, and configure its RSYNC as an output.
STEP 20: Clear all counters and latched status bits.
STEP 21: Set Queue sizes in the Arbiter and reset the queue pointers for the Ethernet and serial interfaces.
STEP 22: After the TSYSCLK and RSYSCLK inputs to the T1/E1/J1 transceivers are stable, the receive and
transmit elastic stores should be reset.
STEP 23: Enable Interrupts as needed.
STEP 24: Initiate link aggregation as discussed in Section 9.8.
STEP 25: Begin handling interrupts and latched status events.
40 of 335