DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 197

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Receive Frame Mode Select (RFM)
Bit 5: Receive B8ZS Enable (RB8ZS)
Bit 4: Receive SLC-96 Enable (RSLC96). Only set this bit to a 1 in D4/SLC-96 framing applications. See Section
10.19
Bit 3: Receive FDL Zero-Destuffer Enable (RZSE). Set this bit to 0 if using the internal HDLC/BOC controller
instead of the legacy support for the FDL. See Section
Bit 2: Reserved. Set to zero for proper operation.
Bit 1: Receive Japanese CRC6 Enable (RJC)
Bit 0: Receive-Side D4 Yellow Alarm Select (RD4YM)
for details.
0 = D4 framing mode
1 = ESF framing mode
0 = B8ZS disabled
1 = B8ZS enabled
0 = SLC-96 disabled
1 = SLC-96 enabled
0 = zero destuffer disabled
1 = zero destuffer enabled
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
—
7
0
TR.T1RCR2
T1 Receive Control Register 2
04h
RFM
6
0
RB8ZS
5
0
RSLC96
197 of 335
10.18
4
0
for details.
RZSE
3
0
—
2
0
RJC
1
0
RD4YM
0
0