DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 225

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 3: CRC4 Sync Counter Bits (CSC5 to CSC2, CSC0). The CRC4 sync counter increments each time the
8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained
synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (TR.E1RCR1.3 =
0). This counter is useful for determining the amount of time the framer has been searching for synchronization at
the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms,
then the search should be abandoned and proper action taken. The CRC4 sync counter rolls over. CSC0 is the
LSB of the 6-bit counter. (Note: The bit next to LSB is not accessible. CSC1 is omitted to allow resolution to
>400ms using 5 bits.) These are read-only, non-latched, real-time bits. It is not necessary to precede the read of
these bits with a write.
Bit 2: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. This is a
read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Bit 0: CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment
word. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive HDLC Reset (RHR). Resets the receive HDLC controller and flushes the receive FIFO. Must be
cleared and set again for a subsequent reset.
Bit 6: Receive HDLC Mapping Select (RHMS)
Bits 5 to 1: Unused, must be set to 0 or proper operation.
Bit 0: Receive SS7 Fill-In Signal Unit Delete (RSFD)
0 = normal operation
1 = reset receive HDLC controller and flush the receive FIFO
0 = receive HDLC assigned to channels
1 = receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)
0 = normal operation; all FISUs are stored in the receive FIFO and reported to the host.
1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without
host intervention.
CSC5
RHR
7
7
0
0
TR.INFO7
Information Register 7 (Real-Time, Non-Latched Register)
30h
TR.H1RC, TR.H2RC
HDLC #1 Receive Control
HDLC #2 Receive Control
31h, 32h
RHMS
CSC4
6
0
6
0
CSC3
—
5
0
5
0
225 of 335
CSC2
—
4
0
4
0
CSC0
—
3
0
3
0
FASSA
—
2
0
2
0
CASSA
—
1
0
1
0
CRC4SA
RSFD
0
0
0
0