DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 63

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7]
(or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or
31:24). If bit reordering is enabled, the incoming 8-bit data stream DT[1:8] is output to the Receive FIFO with the
MSB in RFD[0] and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. DT[1] is the first bit received from the
incoming data stream.
Once all the packet processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit
parallel data stream. The Receive FIFO data is passed on to the Receive FIFO with packet start, packet end,
packet abort, and modulus indications. At a packet end, the 32-bit word may contain 1, 2, 3, or 4 bytes of data
depending on the number of bytes in the packet. The modulus indications indicate the number of bytes in the last
data word of the packet.
Figure 9-12. HDLC Encapsulation of MAC Frame
MSB
Destination Adrs(DA)
Source Adrs(SA)
MAC Client Data
FCS for HDLC
FCS for MAC
Length/Type
Flag(0x7E)
Flag(0x7E)
PAD
Number of Bytes
LSB
46-1500
0 / 2 / 4
63 of 335
4
1
6
6
2