DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 92

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Table 10-12. HDLC Controller Registers
TR.H1TC, HDLC #1 Transmit Control Register
TR.H2TC, HDLC #2 Transmit Control Register
TR.H1RC, HDLC #1 Receive Control Register
TR.H2RC, HDLC #2 Receive Control Register
TR.H1FC, HDLC #1 FIFO Control Register
TR.H2FC, HDLC #2 FIFO Control Register
TR.SR6, HDLC #1 Status Register
TR.SR7, HDLC #2 Status Register
TR.IMR6, HDLC #1 Interrupt Mask Register
TR.IMR7, HDLC #2 Interrupt Mask Register
TR.INFO4, HDLC #1 and #2 Information Register
TR.INFO5, HDLC #1 Information Register
TR.INFO6, HDLC #2 Information Register
TR.H1RPBA, HDLC #1 Receive Packet Bytes Available
TR.H2RPBA, HDLC #2 Receive Packet Bytes Available
TR.H1TFBA, HDLC #1 Transmit FIFO Buffer Available
TR.H2TFBA, HDLC #2 Transmit FIFO Buffer Available
TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4,
HDLC #1 Receive Channel Select Registers
TR.H2RCS1, TR.H2RCS2, TR.H2RCS3, TR.H2RCS4,
HDLC #2 Receive Channel Select Registers
TR.H1RTSBS, HDLC #1 Receive TS/Sa Bit Select
TR.H2RTSBS, HDLC #2 Receive TS/Sa Bit Select
TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4,
HDLC #1 Transmit Channel Select Registers
TR.H2TCS1, TR.H2TCS2, TR.H2TCS3, TR.H2TCS4,
HDLC #2 Transmit Channel Select Registers
TR.H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select
TR.H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select
TR.H1RF, HDLC #1 Receive FIFO Register
TR.H2RF, HDLC #1 Receive FIFO Register
TR.H1TF, HDLC #1 Transmit FIFO Register
TR.H2TF, HDLC #2 Transmit FIFO Register
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
REGISTER
CONTROL AND CONFIGURATION
STATUS AND INFORMATION
MAPPING
FIFOs
92 of 335
General control over the transmit HDLC controllers
General control over the receive HDLC controllers
Sets high watermark for receiver and low
watermark for transmitter
Key status information for both transmit and
receive directions
Selects which bits in the status registers (SR7 and
SR8) cause interrupts
Information about HDLC controller
Indicates the number of bytes that can be read
from the receive FIFO
Indicates the number of bytes that can be written to
the transmit FIFO
Selects which channels are mapped to the receive
HDLC controller
Selects which bits in a channel are used or which
Sa bits are used by the receive HDLC controller
Selects which channels are mapped to the transmit
HDLC controller
Selects which bits in a channel are used or which
Sa bits are used by the transmit HDLC controller
Access to 128-byte receive FIFO
Access to 128-byte transmit FIFO
FUNCTION