DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 303

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Figure 13-20. Transmit Side Boundary Timing (With Elastic Store Disabled)
NOTES:
1) TSYNC is in the output mode (TR.IOCR1.1 = 1.)
2) TSYNC is in the input mode (TR.IOCR1.1 = 0).
3) TCHBLK is programmed to block channel 2.
4) The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS
multiframe-alignment nibble (0000).
5) Shown is a TNAF frame boundary.
Figure 13-21. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz
(With Elastic Store Enabled)
NOTES:
1) The F-bit position in the TSERI data is ignored.
2) TCHBLK is programmed to block channel 24.
TSYSCLK
TCHBLK
TCHCLK
TSSYNC
TSERI
TCHBLK
TCHCLK
TSYNC
TSYNC
TCLKT
TSERI
TSIG
1
2
1
2
3
LSB
CHANNEL 23
D
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8
CHANNEL 1
LSB MSB
CHANNEL 1
303 of 335
CHANNEL 24
MSB
LSB
CHANNEL 2
CHANNEL 2
A
F MSB
B
C
CHANNEL 1
LSB MSB
D