DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 332

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

15.4 JTAG ID Codes
Table 15-2. ID Code Structure
15.5 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included with the DS33R41 design. This test register is the identification register
and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
15.5.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
15.5.2 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which
provides a short path between JTDIn and JTDOn.
15.5.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Ethernet
Mapper
T1/E1/J1
Transceiver
DEVICE
REVISION
ID[31:28]
0000
0000
0000 0000 0110 0010
0000 0000 0010 0010
DEVICE CODE
ID[27:12]
332 of 335
MANUFACTURER’S CODE
000 1010 0001
000 1010 0001
ID[11:1]
REQUIRED
ID[0]
1
1