DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 206

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.
Bit 1: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
Note: During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment. If during this
process an FAS emulator exists, the FAS synchronizer may temporarily align to the emulator. The FASRC will go
active indicating a search for a valid FAS has been activated.
Bit 0: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are
received in error.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Status Register 8 to 1 (SR[8:1]. When set to 1, these bits indicate that an enabled interrupt is active
in the associated T1/E1/J1 status register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0: Status Register 9 (SR9). When set to 1, this bit indicates that an enabled interrupt is active in the
associated T1/E1/J1 status register.
SR8
—
—
7
0
7
0
7
0
TR.INFO3
Information Register 3
12h
TR.IIR1
Interrupt Information Register 1
14h
TR.IIR2
Interrupt Information Register 2
15h
SR7
—
—
6
0
6
0
6
0
SR6
—
—
5
0
5
0
5
0
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SR5
—
—
4
0
4
0
4
0
SR4
—
—
3
0
3
0
3
0
CRCRC
SR3
—
2
0
2
0
2
0
FASRC
SR2
—
1
0
1
0
1
0
CASRC
SR1
SR9
0
0
0
0
0
0