DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 324

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DS33R41

Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet

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14.11 AC Characteristics—Transmit Side
Table 14-16. AC Characteristics—Transmit Side
(V
TCLKT Period
TCLKT Pulse Width
TDCLKI Period
TDCLKI Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width
TSYNC or TSSYNC Setup to
TCLKT or TSYSCLK Falling
TSYNC or TSSYNC Pulse Width
TSERI, TSIG, TPOSI, TNEGI
Setup to TCLKT, TSYSCLK,
TDCLKI Falling
TSERI, TSIG, Hold from TCLKT
or TSYSCLK Falling
TPOSI, TNEGI Hold from TDCLKI
Falling
TCLKT, TDCLKI, or TSYSCLK
Rise and Fall Times
Delay TDCLKO to TPOSO,
TNEGO Valid
Delay TCLKT to TCHBLK,
TCHCLK, TSYNC
Delay TSYSCLK to TCHCLK,
TCHBLK
.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
DD
= 3.3V ±5%, T
PARAMETER
Timing parameters in this table are guaranteed by design (GBD).
TSYSCLK = 1.544MHz.
TSYSCLK = 2.048MHz.
TSYSCLK = 4.096MHz.
TSYSCLK = 8.192MHz.
TSYSCLK = 16.384MHz.
A
= -40°C to +85°C.) (Note 1)
SYMBOL
t
R
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PW
CP
CH
SU
SU
HD
HD
DD
CL
LP
LH
SP
SP
, t
D2
D3
LL
F
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
324 of 335
CONDITIONS
(Figure 14-19
to
MIN
Figure
20
20
20
20
20
20
20
50
20
20
20
14-21)
TYP (E1)
488 (E1)
488 (E1)
648 (T1)
648 (T1)
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
648
448
244
122
61
CP
CP
LP
LP
SP
SP
MAX
25
50
50
22
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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