DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 199

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit B8ZS Enable (TB8ZS)
Bit 6: Transmit SLC-96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a 1 in D4 framing applications.
Must be set to 1 to source the Fs pattern from the TR.TFDL register. See Section
Bit 5: Transmit FDL Zero-Stuffer Enable (TZSE). Set this bit to 0 if using the internal HDLC controller instead of
the legacy support for the FDL.
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit-Side D4 Yellow Alarm Select (TD4YM)
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS)
0 = B8ZS disabled
1 = B8ZS enabled
0 = SLC-96/Fs-bit insertion disabled
1 = SLC-96/Fs-bit insertion enabled
0 = zero stuffer disabled
1 = zero stuffer enabled
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
0 = no stuffing occurs
1 = bit 7 forced to a 1 in channels with all 0s
TB8ZS
7
0
TR.T1TCR2
T1 Transmit Control Register 2
06h
TSLC96
6
0
TZSE
5
0
199 of 335
FBCT2
4
0
FBCT1
3
0
TD4YM
10.19
2
0
for details.
—
1
0
TB7ZS
0
0