DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 218

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit Message-End Event (TMEND)
Bit 5: Receive Packet-End Event (RPE)
Bit 4: Receive Packet-Start Event (RPS)
Bit 3: Receive FIFO Above High-Watermark Condition (RHWM)
Bit 2: Receive FIFO Not Empty Condition (RNE)
Bit 1: Transmit FIFO Below Low-Watermark Condition (TLWM)
Bit 0: Transmit FIFO Not Full Condition (TNF)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
—
7
0
TR.IMR6, TR.IMR7
HDLC # 1 Interrupt Mask Register 6
HDLC # 2 Interrupt Mask Register 7
21h, 23h
TMEND
6
0
RPE
5
0
218 of 335
RPS
4
0
RHWM
3
0
RNE
2
0
TLWM
1
0
TNF
0
0