DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 198

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Japanese CRC6 Enable (TJC)
Bit 6: Transmit F-Bit Pass-Through (TFPT)
Bit 5: Transmit CRC Pass-Through (TCPT)
Bit 4: Transmit Software Signaling Enable (TSSE)
Bit 3: Global Bit 7 Stuffing (GB7S)
Bit 2: TFDL Register Select (TFDLS)
Bit 1: Transmit Blue Alarm (TBL)
Bit 0: Transmit Yellow Alarm (TYEL)
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
0 = F bits sourced internally
1 = F bits sampled at TSERI
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSERI during F-bit time
0 = do not source signaling data from the TR.TSx registers regardless of the TR.SSIEx registers. The
TR.SSIEx registers still define which channels are to have B7 stuffing preformed.
1 = source signaling data as enabled by the TR.SSIEx registers
0 = allow the SSIEx registers to determine which channels containing all 0s are to be bit 7 stuffed
1 = force bit 7 stuffing in all 0-byte channels regardless of how the TR.SSIEx registers are programmed
0 = source FDL or Fs-bits from the internal TR.TFDL register (legacy FDL support mode)
1 = source FDL or Fs-bits from the internal HDLC controller
0 = transmit data normally
1 = transmit an unframed all-ones code at TPOS and TNEG
0 = do not transmit yellow alarm
1 = transmit yellow alarm
TJC
7
0
TR.T1TCR1
T1 Transmit Control Register 1
05h
TFPT
6
0
TCPT
5
0
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TSSE
4
0
GB7S
3
0
TFDLS
2
0
TBL
1
0
TYEL
0
0