DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 24

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

SDMASK[0]
SDMASK[1]
SDMASK[2]
SDMASK[3]
SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDATA[16]
SDATA[17]
SDATA[18]
SDATA[19]
SDATA[20]
SDATA[21]
SDATA[22]
SDATA[23]
SDATA[24]
SDATA[25]
SDATA[26]
SDATA[27]
SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDCLKO
SDA[10]
SDA[11]
SDA[0]
SDA[1]
SDA[2]
SDA[3]
SDA[4]
SDA[5]
SDA[6]
SDA[7]
SDA[8]
SDA[9]
SBA[0]
SBA[1]
NAME
SWE
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
W15
W11
W13
W12
W18
W19
W20
W17
W16
M15
M14
R16
Y11
U12
R13
V13
V12
V11
R12
U11
P19
P20
Y20
V19
U20
U19
Y19
U18
V18
R18
U16
Y17
U17
Y16
V16
V15
R17
P16
Y13
P14
P18
V17
U14
PIN
T15
T13
T11
T12
T18
T20
T19
T17
T16
TYPE
4mA
IO
O
O
O
O
O
SDRAM Write Enable. This active low output enables write operation
and auto precharge.
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the
read/write/precharge operations. Note: All SDRAM operations are
controlled entirely by the DS33R41. No user programming for SDRAM
buffering is required.
SDRAM Data Bus Bits 0 through 31. The 32 pins of the SDRAM data
bus are inputs for read operations and outputs for write operations. At all
other times, these pins are high-impedance.
Note: All SDRAM operations are controlled entirely by the DS33R41. No
user programming for SDRAM buffering is required.
SDRAM Address Bus 0 through 11. The 12 pins of the SDRAM address
bus output the row address first, followed by the column address. The row
address is determined by SDA0 to SDA11 at the rising edge of clock.
Column address is determined by SDA0–SDA9 and SDA11 at the rising
edge of the clock. SDA10 is used as an auto-precharge signal.
Note: All SDRAM operations are controlled entirely by the DS33R41. No
user programming for SDRAM buffering is required.
SDRAM Mask 0 through 3. When high, a write is done for that byte. The
least significant byte is SDATA7 to SDATA0. The most significant byte is
SDATA31 to SDATA24.
SDRAM CLK Out. System clock output to the SDRAM. This clock is a
buffered version of SYSCLKI.
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FUNCTION