DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 8

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ................................................................................................14
Table 7-1. Detailed Pin Descriptions ...................................................................................................................................21
Table 9-1. Clocking Options for the Ethernet Interface .......................................................................................................36
Table 9-2. Reset Functions .................................................................................................................................................39
Table 9-3. Commands Sent and Received on the IMUX Links ...........................................................................................46
Table 9-4. Command and Status for the IMUX for Processor Communication ...................................................................47
Table 9-5. Registers Related to Connections and Queues .................................................................................................50
Table 9-6. Options for Flow Control ....................................................................................................................................51
Table 9-7. Registers Related to the Ethernet Port ..............................................................................................................55
Table 9-8. MAC Control Registers ......................................................................................................................................58
Table 9-9. MAC Status Registers ........................................................................................................................................58
Table 10-1. T1/E1/J1 Transmit Clock Source .....................................................................................................................69
Table 10-2. T1 Alarm Criteria ..............................................................................................................................................71
Table 10-3. E1 Sync/Resync Criteria ..................................................................................................................................72
Table 10-4. E1 Alarm Criteria..............................................................................................................................................73
Table 10-5. T1 Line Code Violation Counting Options ........................................................................................................76
Table 10-6. E1 Line-Code Violation Counting Options........................................................................................................76
Table 10-7. T1 Path Code Violation Counting Arrangements .............................................................................................77
Table 10-8. T1 Frames Out-of-Sync Counting Arrangements.............................................................................................78
Table 10-9. Time Slot Numbering Schemes .......................................................................................................................83
Table 10-10. Idle-Code Array Address Mapping .................................................................................................................84
Table 10-11. Elastic Store Delay After Initialization.............................................................................................................87
Table 10-12. HDLC Controller Registers.............................................................................................................................92
Table 10-13. Transformer Specifications ..........................................................................................................................102
Table 10-14. Transmit Error-Insertion Setup Sequence....................................................................................................110
Table 10-15 Error Insertion Examples...............................................................................................................................110
Table 12-1. Register Address Map....................................................................................................................................118
Table 12-2. Global Ethernet Mapper Register Bit Map .....................................................................................................119
Table 12-3. Arbiter Register Bit Map .................................................................................................................................120
Table 12-4. Serial Interface Register Bit Map ...................................................................................................................121
Table 12-5. Ethernet Interface Register Bit Map ...............................................................................................................123
Table 12-6. MAC Indirect Register Bit Map .......................................................................................................................124
Table 12-7. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) ....................................................................126
Table 12-8. Available IMUX User Commands...................................................................................................................136
Table 12-9. TPD Control ...................................................................................................................................................247
Table 12-10. E1 Mode With Automatic Gain Control Mode Enabled (TLBC.6 = 0)...........................................................248
Table 12-11. E1 Mode With Automatic Gain Control Mode Disabled (TLBC.6 = 1)..........................................................248
Table 12-12. T1 Mode With Automatic Gain Control Mode Enabled (TLBC.6 = 0)...........................................................248
Table 12-13. T1 Mode With Automatic Gain Control Mode Disabled (TLBC.6 = 1) ..........................................................248
Table 14-1. Recommended DC Operating Conditions ......................................................................................................305
Table 14-2. DC Electrical Characteristics..........................................................................................................................305
Table 14-3. Thermal Characteristics .................................................................................................................................306
Table 14-4. Theta-JA vs. Airflow .......................................................................................................................................306
Table 14-5. Transmit MII Interface ....................................................................................................................................307
Table 14-6. Receive MII Interface .....................................................................................................................................308
Table 14-7. Transmit RMII Interface..................................................................................................................................309
Table 14-8. Receive RMII Interface...................................................................................................................................310
Table 14-9. MDIO Interface...............................................................................................................................................311
Table 14-10. Transmit WAN Interface...............................................................................................................................312
Table 14-11. Receive WAN Interface ................................................................................................................................313
Table 14-12. SDRAM Interface .........................................................................................................................................314
Table 14-13. AC Characteristics—Microprocessor Bus ....................................................................................................316
Table 14-14. JTAG Interface .............................................................................................................................................319
Table 14-15. AC Characteristics—Receive Side...............................................................................................................320
Table 14-16. AC Characteristics—Transmit Side..............................................................................................................324
Table 15-1. Instruction Codes for IEEE 1149.1 Architecture.............................................................................................331
Table 15-2. ID Code Structure ..........................................................................................................................................332
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