DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 16

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

4 ACRONYMS AND GLOSSARY
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Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
The register names have been allowed to remain with a “SU.” prefix to avoid register renaming.
Note 2: Previous versions of this document used the term “Line” to refer to the Serial Interface. The register names
have been allowed to remain with a “LI.” prefix to avoid register renaming.
Note 3: The terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
Note 4: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each
125μs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first
followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the
MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals
that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a
2.048MHz clock if they share the same 8kHz component).
TIME SLOT NUMBERING SCHEMES
Time Slot
Channel
Channel
Phone
BERT - Bit Error Rate Tester
DCE - Data Communication Interface
DTE- Data Terminating Interface
FCS - Frame Check Sequence
HDLC - High Level Data Link Control
MAC - Media Access Control
MII - Media Independent Interface
RMII - Reduced Media Independent Interface
WAN - Wide Area Network
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