DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 201

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Software Signaling Insertion Enable for Channels 8 to 1 (CH8 to CH1). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 1: Software Signaling-Insertion Enable for Channels 7 to 1 (CH7 to CH1). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
Bit 0: Upper CAS Align/Alarm Word (UCAW). Selects the upper CAS align/alarm pattern (0000) to be sourced
from the upper 4 bits of the TS1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Software Signaling Insertion Enable for Channels 16 to 9 (CH16 to CH9). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Software Signaling Insertion Enable for Channels 15 to 8 (CH15 to CH8). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
0 = do not source the upper CAS align/alarm pattern from the TR.TS1 register
1 = source the upper CAS align/alarm pattern from the TR.TS1 register
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
CH16
CH15
CH8
CH7
7
0
7
0
7
0
7
0
TR.SSIE1 (T1 Mode)
Software Signaling Insertion Enable 1
08h
TR.SSIE1 (E1 Mode)
Software Signaling Insertion Enable 1
08h
TR.SSIE2 (T1 Mode)
Software Signaling-Insertion Enable 2
09h
TR.SSIE2 (E1 Mode)
Software Signaling Insertion Enable 2
09h
CH15
CH14
CH7
CH6
6
0
6
0
6
0
6
0
CH14
CH13
CH6
CH5
5
0
5
0
5
0
5
0
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CH13
CH12
CH5
CH4
4
0
4
0
4
0
4
0
CH4
CH12
CH11
CH3
3
0
3
0
3
0
3
0
CH3
CH11
CH10
CH2
2
0
2
0
2
0
2
0
CH2
CH10
CH1
CH9
1
0
1
0
1
0
1
0
UCAW
CH1
CH9
CH8
0
0
0
0
0
0
0
0