DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 243

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: MCLK Source (MCLKS). Selects the source of MCLK.
Bit 6: CRC-4 Recalculate (CRC4R)
Bit 5: Signaling Integration Enable (SIE)
Bit 4: Output Data Mode (ODM)
Bit 3: Disable Idle Code Auto Increment (DICAI). Selects/deselects the auto-increment feature for the transmit
and receive idle code array address register. See Section 10.10.
Bit 2: Transmit Clock Source Select Bit 0 (TCSS1)
Bit 1: Transmit Clock Source Select Bit 0 (TCSS0)
Bit 0: Function of the RLOS/LOTC Output (RLOSF)
TCSS1
0
0
1
1
0 = MCLK is source from the MCLK pin
1 = MCLK is source from the TSYSCLK pin
0 = transmit CRC-4 generation and insertion operates in normal mode
1 = transmit CRC-4 generation operates according to G.706 intermediate path recalculation method
0 = signaling changes of state reported on any change in selected channels
1 = signaling must be stable for three multiframes in order for a change of state to be reported
0 = pulses at TPOSO and TNEGO are one full TCLKO period wide
1 = pulses at TPOSO and TNEGO are one-half TCLKO period wide
0 = addresses in TR.IAAR register automatically increment on every read/write operation to the TR.PCICR
register
1 = addresses in TR.IAAR register do not automatically increment
0 = receive loss of sync (RLOS)
1 = loss-of-transmit clock (LOTC)
MCLKS
TCSS0
7
0
0
1
0
1
TR.CCR1
Common Control Register 1
70h
The TCLKT pin is always the source of transmit clock.
Switch to the clock present at RCLKn when the signal at the TCLKT pin
fails to transition after 1 channel time.
Use the scaled signal present at MCLK as the transmit clock. The
TCLKT pin is ignored.
Use the signal present at RCLKn as the transmit clock. The TCLKT pin
is ignored.
CRC4R
6
0
SIE
5
0
Transmit Clock Source
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ODM
4
0
DICAI
3
0
TCSS1
2
0
TCSS0
1
0
RLOSF
0
0