DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 253

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 6: Set to zero for normal operation.
Bits 5, 3, 1: Automatic Gain Control Target Bits 2, 1, 0 (AGCT2, AGCT1, AGCT0). These three bits adjust the
target amplitude of the waveform when using Automatic Gain Control (AGCE = 0). The adjustment for each setting
is listed below:
Standard Settings for non-automatic gain mode:
Bits 4 and 2: Slew Rate Reduction Control Bits 1 and 0 (SRR1 and SRR0). These bits are a binary weighted
array that can be set to make the waveform "colder" (i.e., increase rise time, reduce overshoot).
Bit 0: Slew Rate Increase "B" (SRIB0). This bit, when set, makes the waveform a bit hotter (different method than
Group 1). Not much effect from this bit should be expected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6, 5, 4, 2, 1, and 0: Unused, must be set to zero for proper operation.
Bits 7 and 3: Slew Rate Increase "A" Control Bits 4 and 3 (SRIA4 and SRIA3). These bits (together with the
SRIA0–SRIA2 in the SRC1 register) form a 5-bit binary weighted array used to increase the slew rate of the output
waveform. However, SRIA3 and SRIA4 have the same weighting. SRIA4 (F2h, bit 7) is the MSB, and SRIA0 (F0h,
bit 5) is the LSB. The more of this array that is set, the "hotter" (i.e., faster rise times, more overshoot) the
waveform.
AGCT2
0
0
0
0
1
1
1
1
SRIA4
AGCT1
—
7
0
7
0
0
0
1
1
0
0
1
1
TR.PSA1
Pulse Shape Adjustment 1
F1h
TR.PSA2
Pulse Shape Adjustment 2
F2h
AGCT0
—
—
6
0
6
0
0
1
0
1
0
1
0
1
AGCT2
—
5
0
5
0
AGCAC (in
hex)
0Ah
2Ah
00h
02h
08h
20h
22h
28h
253 of 335
SRR1
—
4
0
4
0
% change in amplitude
AGCT1
0% (default)
SRIA3
3
0
3
0
+ 10%
+ 15%
+ 35%
- 23%
- 15%
+ 6%
- 8%
SRR0
—
2
0
2
0
AGCT0
—
1
0
1
0
SRIB0
—
0
0
0
0