DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 149
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Packet Count (TPC[7:0]). Eight bits of 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Packet Count (TPC[15:8]). Eight bits of 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Packet Count (TPC[23:16]). These 24 bits indicate the number of packets extracted from
the Transmit FIFO and output in the outgoing data stream.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Byte Count (TBC[7:0]). Eight bits of 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Byte Count (TBC[15:8]). Eight bits of 32-bit value. Register description below.
TPC15
TPC23
TBC15
TPC7
TBC7
7
0
7
0
7
0
7
0
7
0
TPC14
TPC22
TBC14
TPC6
TBC6
6
0
6
0
6
0
6
0
6
0
LI.TPCR0
Transmit Packet Count Byte 0
0CCh
LI.TPCR1
Transmit Packet Count Byte 1
0CDh
LI.TPCR2
Transmit Packet Count Byte 2
0CEh
LI.TBCR0
Transmit Byte Count Byte 0
0D0h
LI.TBCR1
Transmit Byte Count Byte 1
0D1h
TPC13
TPC21
TBC13
TPC5
TBC5
5
0
5
0
5
0
5
0
5
0
TPC12
TPC20
TBC12
149 of 335
TPC4
TBC4
0
0
0
0
0
4
4
4
4
4
TPC11
TPC19
TBC11
TPC3
TBC3
3
0
3
0
3
0
3
0
3
0
TPC10
TPC18
TBC10
TPC2
TBC2
2
0
2
0
2
0
2
0
2
0
TPC17
TPC1
TPC9
TBC1
TBC9
1
0
1
0
1
0
1
0
1
0
TPC16
TPC0
TPC8
TBC0
TBC8
0
0
0
0
0
0
0
0
0
0
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