DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 70

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.4 T1 Framer/Formatter Control and Status
The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the transceiver has been initialized, the
control registers only need to be accessed when there is a change in the system configuration. There are two
receive control registers (TR.T1RCR1 and TR.T1RCR2), two transmit control registers (TR.T1TCR1 and
TR.T1TCR2), and a common control register (TR.T1CCR1). Each of these registers is described in this section.
10.4.1 T1 Transmit Transparency
The software signaling insertion-enable registers, TR.SSIE1–TR.SSIE4, can be used to select signaling insertion
from the transmit signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the TR.SSIEx register
allows signaling data to be sourced from the signaling registers for that channel.
In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the
channels. If a DS0 is programmed to be clear, no robbed-bit signaling is inserted nor does the channel have bit 7
stuffing performed. However, in the D4 framing mode, bit 2 is overwritten by a 0 when a Yellow Alarm is
transmitted. Also, the user has the option to globally override the TR.SSIEx registers from determining which
channels are to have bit 7 stuffing performed. If the TR.T1TCR1.3 and TR.T1TCR2.0 bits are set to 1, then all 24
T1 channels have bit 7 stuffing performed on them, regardless of how the TR.SSIEx registers are programmed. In
this manner, the TR.SSIEx registers are only affecting the channels that are to have robbed-bit signaling inserted
into them.
10.4.2 AIS-CI and RAI-CI Generation and Detection
The device can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with
and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI
T1.403.
The AIS-CI code (alarm indication signal-customer installation) is the same for both ESF and D4 operation. Setting
the TAIS-CI bit in the TR.T1CCR1 register and the TBL bit in the TR.T1TCR1 register causes the device to
transmit the AIS-CI code. The RAIS-CI status bit in the TR.SR4 register indicates the reception of an AIS-CI signal.
The RAI-CI (remote alarm indication-customer installation) code for T1 ESF operation is a special form of the ESF
Yellow Alarm (an unscheduled message). Setting the RAIS-CI bit in the TR.T1CCR1 register causes the device to
transmit the RAI-CI code. The RAI-CI code causes a standard Yellow Alarm to be detected by the receiver. When
the host processor detects a Yellow Alarm, it can then test the alarm for the RAI-CI state by checking the BOC
detector for the RAI-CI flag. That flag is a 011111 code in the 6-bit BOC message.
The RAI-CI code for T1 D4 operation is a 10001011 flag in all 24 time slots. To transmit the RAI-CI code the host
sets all 24 channels to idle with a 10001011 idle code. Since this code meets the requirements for a standard T1
D4 Yellow Alarm, the host can use the receive channel monitor function to detect the 100001011 code whenever a
standard Yellow Alarm is detected.
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