DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 150

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DS33R41

Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Byte Count (TBC[23:16]). Eight bits of 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Byte Count (TBC[31:24]). These 32 bits indicate the number of packet bytes inserted in the
outgoing data stream.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Manual Error Insertion (TMEI). A 0-to-1 transition inserts a single error in the Transmit direction.
Register Name:
Register Description:
Register Address:
Bit 0: Transmit PMU Update (TPMUU). This signal causes the transmit cell/packet processor block performance
monitoring registers (counters) to be updated. A 0-to-1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance monitoring
counters for the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit 0: Transmit PMU Update Status (TPMUS). This bit is set when the Transmit PMU Update is completed. This
bit is cleared when TPMUU is reset.
Bit #
Name
Default
Bit #
Name
Default
TBC23
TBC31
7
0
7
0
7
0
7
0
7
0
TBC22
TBC30
6
0
6
0
6
0
6
0
6
0
LI.TBCR2
Transmit Byte Count Byte 2
0D2h
LI.TBCR3
Transmit Byte Count Byte 3
0D3h
LI.TMEI
Transmit Manual Error Insertion
0D4h
LI.THPMUU
Serial Interface Transmit HDLC PMU Update Register
0D6h
LI.THPMUS
Serial Interface Transmit HDLC PMU Update Status Register
0D7h
TBC21
TBC29
5
0
5
0
5
0
5
0
5
0
TBC20
TBC28
150 of 335
0
0
0
4
4
4
4
0
4
0
TBC19
TBC27
3
0
3
0
3
0
3
0
3
0
TBC18
TBC26
2
0
2
0
2
0
2
0
2
0
TBC17
TBC25
1
0
1
0
1
0
1
0
1
0
TBC16
TBC24
TPMUU
TPMUS
TMEI
0
0
0
0
0
0
0
0
0
0

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