DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 182

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
001Ch:
Bit #
Name
Default
001Dh:
Bit #
Name
Default
001Eh:
Bit #
Name
Default
001Fh:
Bit #
Name
Default
Bits 31 to 16: Pause Time (PT[15:00]). These bits are used for the Pause Time Field in transmitted Pause
Frames. This value is the number of time slots the remote node should wait prior to transmission.
Bit 1: Flow Control Enable (FCE). When set to 1, the MAC automatically detects pause frames and will disable
the transmitter for the requested pause time.
Bit 0: Flow Control Busy (FCB). The host can set this bit to 1 in order to initiate transmission of a pause frame.
During transmission of a pause frame, this bit remains set. The device will clear this bit when transmission of the
pause frame has been completed. The user should read this bit and ensure that this bit is equal to zero prior to
initiating a pause frame.
Reserved
Reserved
PT15
PT07
31
23
15
07
0
0
0
0
Reserved
Reserve
PT14
PT06
06
30
22
14
d
0
0
1
0
SU.MACFCR
MAC Flow Control Register
001Ch (indirect)
Reserved
Reserved
PT13
PT05
05
29
21
13
0
0
0
0
Reserved
Reserved
182 of 335
PT12
PT04
28
20
12
04
0
1
0
0
Reserved
Reserved
PT11
PT03
27
19
11
03
0
0
0
0
Reserved
Reserved
PT10
PT02
26
18
10
02
0
0
0
0
Reserved
PT09
PT01
FCE
25
17
09
01
1
0
0
0
Reserved
PT08
PT00
FCB
00
24
16
08
0
0
0
0